1. Field of the Invention
The present invention relates to a liquid crystal display apparatus and its liquid crystal drive circuit which enables a liquid crystal panel to display graphic data even with a resolution different from a resolution of the liquid crystal panel.
2. Description of Related Art
As a conventional liquid crystal drive circuit, there is a TFT liquid crystal data driver HD66330T which is 192-channel 64-pixelxc3x976-bit, described in pages 952-954, Hitachi LCD controller/driver LSI data book (Hitachi, Ltd., published March 1994).
FIG. 13 is a schematic illustration showing an internal structure of HD66330T. An operation of the conventional liquid crystal driver circuit will now be explained with reference to FIG. 13.
In FIG. 13, 1301 indicates a latch address control circuit, 1302 indicates a latch circuit (1), 1303 indicates a latch circuit (2), 1304 indicates a liquid crystal applied voltage generation circuit, 1305 indicates a clock for latching input display data, 1306 indicates a line clock with a period of one line, 1307 indicates the input display data, 1308 indicates latch signals, 1309 indicates latch circuit (1) output data, 1310 indicates latch circuit (2) output data, 1311 indicates base voltages for providing bases of the liquid crystal apply voltages, 1312 indicates liquid crystal applied voltage outputs, and 1313 indicates a chip enable signal.
First, the latch address control circuit 1301 generates the latch signals 1308 for latching the input display data 1307 successively, the input display data 1307 being inputted in synchronization with the clock 1305. The latch circuit (1) 1302 latches the input display data 1307 of 3-channel 1 pixelxc3x976-bit successively in accordance with the latch signals 1308. Data of 192-channel 64-pixelxc3x976-bit latched by the latch circuit (1) 1302 are then latched by the latch circuit (2) 1303 in synchronization with the line clock 1306. The data latched by the latch circuit (2) 1303 are decoded pixel by pixel. The applied voltages are generated according to the decoding results, and are outputted from the liquid crystal apply voltage generation circuit 1304.
FIG. 14 schematically illustrates a liquid crystal display apparatus with HD66330T, the conventional liquid crystal driver circuit. The prior art will now be explained with reference to FIG. 14.
In FIG. 14, 1401-U indicates an upper part of a liquid crystal drive circuit comprising an array of the conventional liquid crystal drive circuits, 1401-L indicates a lower part of a liquid crystal drive circuit comprising an array of the conventional liquid crystal drive circuits, 1402 indicates a scanning driver, 1403 indicates a controller ,1404 indicates a liquid crystal display panel, 1405 indicates input RGB display data to be inputted to the liquid crystal display apparatus ,1406 indicates a dot clock, 1407 indicates a horizontal sync signal, 1408 indicates a vertical sync signal, 1409 indicates a display timing signal, 1410-U indicates upper display data, 1410-L indicates lower display data, 1411-U indicates an upper clock generated by halving a frequency of the dot clock, 1411-L indicates a lower clock generated by halving a frequency of the dot clock, 1412 indicates the first line marker indicating a start of the scanning operation and 1413 indicates a shift clock with the same frequency as that of the horizontal sync signal.
As shown in FIG. 14, the controller 1403 divides the dot clock 1406 into one half of the original frequency, and outputs, the upper clock 1411-U and the lower clock 1411-L. The controller 1403 also selects the input display data 1405 having every RGB data of odd and even number pixels, and outputs the R data of the odd number pixels, the B data of the odd number pixels and the G data of the even number pixels as the upper display data 1410-U, and outputs the G data of the odd number pixels, the R data of the even number pixels and the B data of the even number pixels as the lower display data 1410-L.
The liquid crystal drive circuits 1401-U and 1401-L latch the display data 1410-U and 1410-L outputted from the controller 1403 at trailing edges of the clocks 1411-U and 1411-L, and output the liquid crystal applied voltages to every pixel at the leading edge of the line clock 1306.
The scanning driver 1402 selects the lines in accordance with the first line marker 1412 and the shift clock 1413 to realize a display on the liquid crystal panel. Accordingly, a train of the input display data 1405 is displayed as they are on the liquid crystal panel. The input display data 1405 usually have the same resolution as that of the liquid crystal panel 1404, and are displayed over the whole display area of the liquid crystal panel.
In the prior art described above, the display could not be carried out properly when the display data with a lower resolution than that of the liquid crystal panel are to be inputted. FIG. 15 is a schematic illustration of a case where the display data with a lower resolution than that of the liquid crystal panel are to be inputted.
When the display data 1405 with a lower resolution than that of the liquid crystal panel are inputted, no data is latched at the liquid crystal drive circuits located at right ends of the liquid crystal drive circuits 1401-U and 1401-L because there are less display data in the lateral direction and effective display area for the input display data 1405 is displayed at the upper left. A position of such a display may not be well balanced with respect to the liquid crystal panel 1404. Furthermore, the data display area in such a display would be smaller compared to the total display area of the liquid crystal panel 1404. Accordingly, a large display area may not be utilized effectively due to the increase of the ineffective display area if the liquid crystal panel of a higher resolution is used. These are presented as problems.
Normally, there are data in the ineffective display interval which occurs between the effective display interval and a pulse of the line clock 306. As shown in FIG. 15, the problems of not being able to latch the data in the right end side of the driver as described above may also be observed when the total number of the pixels in one line is less than a number of pixels in the lateral direction of the liquid crystal panel 1404, even if the data during the ineffective display interval are additionally used.
The object of the present invention is to provide a liquid crystal drive circuit enabling a decrease in the ineffective display area by expanding the display data, and to display the display data in the middle part of the liquid crystal panel even when the display data with a lower resolution than that of the liquid crystal panel are to be inputted.
General features of typical embodiments of the inventions disclosed in the present application will now be explained as follows.
The present invention in the first embodiment provides a liquid crystal drive circuit comprising: a latch address control circuit for generating a latch signal or a plurality of latch signals in parallel according to a parallel latch number control signal specifying a number of the display data to be latched in parallel; a data control circuit for controlling display data to be latched in parallel according to the control signal; a the-first hold circuit for latching the display data controlled by the data control circuit for an amount of output data lines according to the latch signals,. and holding the latched data; a second hold circuit for latching the display data held in the first hold circuit in parallel for an amount of the output data lines according to a horizontal sync signal, and holding the latched data; and a gray scale voltage output circuit for selecting gray scale voltages generated by dividing base voltages in accordance with the display data held in the second hold circuit, and buffering and outputting the selected data.
Further, in the second embodiment, the present invention provides a liquid crystal drive circuit which further comprises a third hold circuit for latching the display data held in the second hold circuit in parallel for an amount of the output data lines according to a horizontal sync signal with a frequency M/N times (M, N are natural numbers and Mxe2x89xa7N) higher than a frequency of the horizontal sync signal for the input display data, holding the latched data, and outputting the display data held therein to the gray scale voltage output circuit, replacing the second hold circuit in the first embodiment.
Alternatively, the parallel latch number control signal in the first and second embodiments may indicate information including at least one of parallel latch number information for a lateral data expansion display and parallel latch number information for a centering display; and the latch address control circuit may comprise latch signal generation means for generating pulses for the latch signals, a number of the pulses corresponding to the control signal; latch address select means for selecting the hold circuit addresses where the display data are to be held; and decode means for decoding outputs of the latch signal generation means and the latch address select means to convert them into the latch signal.
Further, in the first and second embodiments, the parallel latch number control signal may indicate parallel latch number information for a lateral data expansion display; and the data control circuit may comprise a plurality of data select circuits provided in equal number to the parallel latch number for the lateral data expansion display into which a plurality of the pixels of the display data are latched in parallel; and data select control means for distributing the display data to every one of the data select circuits and controlling every one of the data select circuits to select one of a plurality of the display data in accordance with the hold circuit addresses and the parallel latch number control signal.
Further, the liquid crystal drive circuits in the first and second embodiments may further comprise chip enable signal output control means for detecting a number of the latch signals yet to be outputted, and outputting information regarding the detected number as a chip enable signal to the other liquid crystal drive circuit.
The chip enable output control means may detect a number of said latch signals yet to be outputted, the number being equal to the maximum parallel latch number or less.
Further, the liquid crystal drive circuits in the first and second embodiments may further comprise chip enable input control means for accepting a chip enable signal indicating information regarding a number of the latch signals yet to be outputted, and determining a number of the display data in the first parallel latch according to the chip enable signal and the first parallel latch number control signal.
Here, it is preferable to have the chip enable input control means which accepts the chip enable signal input, and prohibits the data latch operation when a number, which is calculated by subtracting the latch signal number to-be-outputted indicated in the chip enable signal from the parallel latch data number indicated in the first parallel latch number control signal, is equal to 0 or less, and sets the number calculated as the first parallel latch display data number when the number calculated is equal to 1 or more.
Further, the present invention makes it possible to provide a liquid crystal display apparatus comprising: control means for outputting a liquid crystal horizontal sync signal with a frequency N (Nxe2x89xa71) times larger than a frequency of the input horizontal sync signal; a scanning circuit for scanning successively according to said liquid crystal horizontal sync signal; and M (M is an integer equal to 1 or more) number of liquid crystal drive circuits of the present invention; wherein the input display data is displayed at the liquid crystal panel with at least one of an expansion display format and a centering display format.